2.1. HBM2E in Intel Agilex® 7 M-Series Devices
Intel Agilex® 7 M-Series devices incorporate Intel’s Embedded Multi-Die Interconnect Bridge (EMIB) technology to implement a silicon bridge between HBM2E DRAM memory and the Universal Interface Block Subsystem (UIBSS). The UIB subsystem contains the HBM2E controller (HBMC), physical-layer interface (PHY), and I/O ports to interface to the HBM2E stack. The FPGA core accesses the UIB through the integrated hard memory network-on-chip (NoC).
As illustrated in the figure below, each Intel Agilex® 7 M-Series device contains a single universal interface bus per HBM2E interface, supporting 8 independent channels. The HBM2E channel interface operates in pseudo-channel mode, providing a separate read and write command queue for each of the two pseudo-channels.
The user interface to the hard memory NoC uses the AXI4 protocol; the hard memory NoC also communicates with the UIB using the AXI4 protocol. Each HBM2E controller provides sixteen AXI interfaces, one AXI interface for each HBM2E pseudo-channel. HBM2E DRAM densities of 8GB and 16GB are supported.