High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 M-Series FPGA IP User Guide

ID 773264
Date 12/04/2023
Public
Document Table of Contents

A. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Intel® Quartus® Prime Software Flow

This section describes how to assign physical locations to the initiators using the Interface Planner tool and how to simulate your HBM2E design.