High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 M-Series FPGA IP User Guide

ID 773264
Date 12/04/2023
Public
Document Table of Contents

5.5.3. ECC Error Counters Register

This per-pseudo-channel register counts the number of single-bit errors and double-bit errors detected by the HBM controller.

These counts can be used by software to track the reliability of the memory device. To read the ECC error counters register, issue a read command to the offset 32’h0560 for pseudo-channel 0 and 32’h0860 for pseudo-channel 1.

Table 36.  ECC Error Counters Register
Bits Access Default Name Description
14:0 RW1C 15’h0 SBE_ERRCNT Number of correctable single-bit errors in pseudo-channel read responses detected by the HBM controller, since power up or counter reset. This counter saturates at maximum count. Any error after maximum count sets the overflow bit.
15 RW1C 1’b0 Reserved Reserved.
30:16 RW1C 15’h0 DBE_ERRCNT Number of uncorrectable (double-bit) errors in pseudo-channel read responses detected by the HBM controller, since power up or counter reset. This counter saturates at maximum count. Any error after maximum count sets the overflow bit.
31 RW1C 1’b0 Reserved Reserved.