High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 M-Series FPGA IP User Guide

ID 773264
Date 12/04/2023
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5.1. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP High Level Block Diagram

The following figure shows a high-level block diagram of the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP per Pseudo Channel. The IP communicates with user logic through the AXI protocol.
Figure 14. High Level Block Diagram of HBM2E Implementation