5.4. Platform Designer-Only Interface
The number of HBM2E target NoC interfaces available in the Platform Designer is determined by the number of channels enabled on the HBM2E IP. Each pseudo-channel has dedicated NoC target hardware, and that NoC target includes a target NoC interface that features in the Platform Designer patch panel. The HBM2E IP exposes a target NoC interface for each AXI-Lite NoC target bridge enabled by the IP. These NoC targets provide access to control and status registers of a predefined pair of HBM2E channels. The naming convention for HBM2E pseudo-channel target NoC interfaces follows the pattern of t_ch<x>_u<y>_axi4noc, where x is the channel number and y is the pseudo-channel number. The HBM2E controller register access target NoC interface naming is t_ch<z>_ch<z+1>_sb_axi4noc, where z is 0, 2, 4 or 6.