5.5. User Accesses to the HBM2E Controller
You must enable the AXI4-Lite interface to access the control and status registers for diagnostic or debugging purposes. You can achieve this by specifying the Number of AXI4-Lite interfaces option when configuring the NoC Initiator IP.
The allocation of register offsets from the base of the channel's register space are as follows:
- Initialization control : 32’h0010
- Initialization status : 32’h0014
- Thermal Status : 32’h0100
- ECC Error counters (PC0) : 32’h0560
- ECC Error counters (PC1) : 32’h0860
These addresses are offsets from the start of the HBM channel's register block. Each HBM sideband NoC target provides access to the registers of two channels, at offsets 32'h0000 and 32'h10000 from the base address that you have set for the NoC target in your NoC initiator's address map.