High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 M-Series FPGA IP User Guide

ID 773264
Date 12/04/2023
Public
Document Table of Contents

7.1. Debugging Guidelines for High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP

Follow these guidelines when commencing to debug calibration problems with the HBM2E IP:

  • Check the power supplies related to the HBM2E circuitry and verify that all are at the correct voltage levels.
  • Check the universal interface bus (UIB) power.
  • Check the UIB reference clock and its board connectivity. Verify the quality of the clock signal.
  • Check that the PLL clock source meets its specifications, including its jitter specification.
  • Check the circuit board to ensure that all reference clocks are toggling at the correct frequencies before configuring the device.
  • Check the HBM2E device calibration using an out-of-the-box design example.
  • Check the design using reduced specifications.