High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 M-Series FPGA IP User Guide

ID 773264
Date 12/04/2023
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5.2.3. Asynchronous HBM2E Controller Signals

Table 21.  Thermal Status Signals
Signal Direction Description
hbm_cattrip Output

Device Catastrophic Trip (CATTRIP): Reflects the catastrophic trip indication reported by the HBM2E device.

hbm_temp Output[2:0]

Device Temperature Compensated Refresh Value (TEMP): Reflects the temperature compensated refresh band reported by the HBM2E device. Refer to the device specification for temperature code definitions.

Table 22.  Level-sensitive Interrupt Signals
Signal Direction Description
ch0_u0_wmc_intr Output Level-sensitive interrupts which indicate that an error or diagnostic event has occurred on the associated pseudo-channel. Your design should interrogate the pseudo-channel's interrupt status registers to identify the condition that caused the interrupt.
ch0_u1_wmc_intr Output
ch1_u0_wmc_intr Output
ch1_u1_wmc_intr Output
ch2_u0_wmc_intr Output
ch2_u1_wmc_intr Output
ch3_u0_wmc_intr Output
ch3_u1_wmc_intr Output
ch4_u0_wmc_intr Output
ch4_u1_wmc_intr Output
ch5_u0_wmc_intr Output
ch5_u1_wmc_intr Output
ch6_u0_wmc_intr Output
ch6_u1_wmc_intr Output
ch7_u0_wmc_intr Output
ch7_u1_wmc_intr Output