High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 M-Series FPGA IP User Guide

ID 773264
Date 12/04/2023
Public
Document Table of Contents

5.5.1. Initialization Control Register and Initialization Status Register

The Initialization control and status registers provide feedback on progress of the reset sequence.

To read the status of these registers, issue a read command to the offset 32’h0010 for the control register and 32’h0014 for the status register.

Table 33.  Initialization Control Register
Bits Access Name Description
15:0 RO Reserved Reserved.
16 RO AXI FenceReq Asserted by the UIB subsystem controller during the part of the reset sequence in which the HBM controller cannot accept AXI4 memory transactions. If user logic issues memory transactions to the memory controller while this bit is asserted, the resulting system state is undefined.
31:17 RO Reserved Reserved.
Table 34.  Initialization Status Register
Bits Access Name Description
0 RO INITPROG Indicates that a reset sequence is in progress. At the end of the reset sequence one of INITSTS_PASS or INITSTS_FAIL is asserted.
1 RO INITSTS_PASS

0: when INITPROG=1

1: Reset sequence completed successfully

Mutually exclusive with INITSTS_FAIL

2 RO INITSTS_FAIL

0: when INITPROG=1

1: Reset sequence failed

Mutually exclusive with INITSTS_PASS

31:3 RO Reserved Reserved.