Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 7/05/2023

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6. Simulating NoC Designs

Behavioral, non-cycle accurate simulation of the NoC is available, in combination with your logic as either RTL or as a functional (non-timing) gate-level netlist. You can use these simulation methods to verify correct specification of the connectivity and addressing. However, you cannot model the throughput, latency, or traffic congestion on the hard memory NoC.

As with any other Intel FPGA IP, you can generate simulation models for NoC-related IP during IP HDL generation. Refer to Introduction to Intel FPGA IP Cores for instructions on incorporating these models into your simulation netlist and generating the appropriate simulation scripts.

There is an optional early simulation flow in which you instantiate and define connectivity of the NoC IP in Platform Designer and perform early RTL simulation without having any requirement to run Analysis & Elaboration. If you define NoC connectivity and addressing in Platform Designer, you must still define the same NoC connectivity and addressing in the NoC Assignment Editor for Intel® Quartus® Prime compilation.

After performing these initial simulation tasks, you must then add NoC connectivity and address mapping to your simulation netlist, as Adding NoC Connectivity and Address Mapping to the Simulation Netlist describes next.