Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 7/05/2023

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3.6.5. Initiator and Target Bandwidth Considerations

On the FPGA fabric side of the hard memory NoC, you can calculate maximum initiator bandwidth by multiplying the user clock frequency by the width of the initiator data bus that is typically 32 Byte.

The bandwidth for NoC targets depends on the type and configuration of memory you use, such as HBM2e or DDR5 memory.

Refer to the High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 FPGA IP User Guide for HBM2e specifications. Refer to the External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide for external memory specifications (such as DDR4, DDR5, and LPDDR5).