Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 7/05/2023
Public

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4.5.2. Using the NoC Assignment Editor

The NoC Assignment Editor in the Intel® Quartus® Prime Pro Edition software allows you to make logical assignments for hard memory NoC-related blocks in your design. These assignments include grouping, connectivity, address mapping, and bandwidth requirements.

Note: Regardless of whether you instantiate the NoC IP using Platform Designer or directly in RTL, the netlist does not include the connections between NoC initiators, targets, and the clock control. If your design uses the NoC Assignment Editor connection flow, as NoC Design Flow Options describes, you must specify these connections using the NoC Assignment Editor. If your design uses the Platform Designer connection flow, as NoC Design Flow Options describes, you specify these connections in Platform Designer. The design’s .qip file stores the connection and address mapping assignments. The NoC Assignment Editor automatically reads these connection assignments and displays them as read-only assignments.
Figure 21. Network on Chip (NoC) Assignment Editor

After making assignments in the NoC Assignment Editor, you click Save to store the assignments in the Intel® Quartus® Prime settings file (.qsf). You must successfully complete Analysis & Elaboration before using the NoC Assignment Editor.

To access the NoC Assignment Editor, click Assignments > Network on Chip (NoC) Assignment Editor.

Specify assignments on the following NoC Assignment Editor tabs:

  • Group tab—specifies the Group Name of the NoC initiators and targets.
  • Connection tab—specifies the connections between NoC initiators and targets or SSM elements.
  • Attributes tab—specifies address mapping, bandwidth requirements, and transaction sizes for each connection.

The tabs appear in order of priority. The assignments made on the Group tab affect the assignments available in the Connection tab. The assignments made on the Connection tab affect the assignments available in the Attributes tab.

Complete the assignments on each tab in order before moving to the next tab.

If your design uses the Platform Designer connection flow, as NoC Design Flow Options describes, the connection and address map assignments that you create in Platform Designer automatically appear in the NoC Assignment Editor. However, you must create group assignments before proceeding with compilation. To allow analysis of your design for possible traffic congestion, you must also create bandwidth and transaction size assignments.