Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 7/05/2023

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Document Table of Contents

4.4.1. General NoC IP Connectivity Guidelines

To create a hard memory NoC design, you instantiate NoC initiators (for fabric and for HPS AXI4 managers), NoC targets in memory IP (for fabric and HPS AXI4 managers) and NoC clock control IP in your Platform Designer system or in your RTL netlist. Connect these IP blocks to external pins or FPGA core logic, as this section of the document describes in detail.

There are two supported flows for making connections between NoC initiators and targets, as NoC Design Flow Options describes. In the Platform Designer connection flow, you connect NoC initiators to NoC targets in Platform Designer, and then generate the HDL for your system. Note that when using the Platform Designer connection flow, Platform Designer stores the connections in the system .qip file and are in the generated HDL. In the NoC Assignment Editor Connection flow, you do not connect NoC initiators to NoC targets within either Platform Designer or RTL. Instead, you run Analysis & Elaboration and then make these connections in the NoC Assignment Editor. The following sections provide details on connecting NoC IP using both design flows.