Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 7/05/2023
Public

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6.2. Generating a Simulation Registration Include File (NoC Assignment Editor Connection Flow)

To generate a simulation registration include file for the NoC Assignment Editor connection flow, follow these steps:

Note: These steps do not apply to the Platform Designer connection flow. For this flow, refer to Generating a Simulation Registration Include File (Platform Designer Connection Flow).
  1. Specify your NoC grouping, initiator-to-target connectivity, and base addressing in the NoC Assignment Editor, as Using the NoC Assignment Editor describes. Alternatively, you can specify these assignments directly in the .qsf.
  2. Re-run Analysis & Elaboration or perform a full compilation. This step allows the Compiler to read your assignments and create a simulation registration include file that contains the information that simulation requires to reflect your connectivity specifications. The registration include file contains one registration statement for each initiator-to-target connection, specifying the start address and the size of that connection’s address range.
    Note: If you update any of these assignments in the NoC Assignment Editor, or modify them directly in the .qsf, you must re-run Analysis & Elaboration or perform a full compile to update this simulation registration include file.