Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 7/05/2023

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Document Table of Contents

4.1. Hard Memory NoC Design Flow Overview

Creating a hard memory NoC design in the Intel® Quartus® Prime software consists of the following high level steps that this chapter describes in detail:

Figure 18. Hard Memory NoC Design Flow

  1. Instantiate and configure NoC-related IP, including the NoC Initiator Intel FPGA IP, the HBM2E IP or external memory IP that contain the NoC targets, the NoC Clock Control Intel FPGA IP, and (if using) the Hard Processor System Intel Agilex® 7/Agilex 9 FPGA IP in your design using Platform Designer or directly in design RTL.
    Note: If your design includes the Hard Processor System Intel Agilex 7 /Agilex 9 FPGA IP, you must configure and instantiate this IP using Platform Designer.
  2. Define logical constraints for NoC grouping, connectivity, addressing, and performance targets.
  3. (Optional) Perform RTL simulation of the NoC design, as Simulating NoC Designs describes.
  4. (Recommended) Run Analysis & Synthesis and then assign physical locations for NoC elements and other periphery elements, as Make Physical Assignments Using Interface Planner describes. Otherwise, the Intel® Quartus® Prime Fitter makes the physical assignments during design compilation.
  5. Compile your design and review the placement and performance reports, as Compiling the NoC Design describes.