Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 7/05/2023
Public

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8.1.2.3. NoC Initiator Intel FPGA IP AXI4 Lite User Interface Signals

There are three types of AXI4 Lite interfaces that you may have in your design:

  1. The NoC subsystem uses an AXI4 Lite target that you can access to read performance monitoring registers.
  2. The HBM2e IP optionally uses an AXI4 Lite target that provides access to the HBM2e memory controller's configuration and status registers.
  3. The EMIF IP uses a AXI4 Lite target that connects to the I/O subsystem (IOSSM) and provides the following functionality:
    • Through the IOSSM Mailbox, provides access to the HMC (hard memory controller) CSRs.
    • Through the IOSSM Mailbox, provides capability for discovery (which EMIF ID is in the same GPIO-B bank as this IOSSM).
    • Through the IOSSM Mailbox, provides API to read calibration diagnostic info.
    • Through the IOSSM Mailbox, provides API to read PLL lock status.
    • Provides direct access to (reading from or writing to) PHY registers.

The AXI4 Lite interface is primarily for relatively low-bandwidth sideband operations. Conversely, the AXI4 interface is primarily for high-bandwidth, mainband operations.

The signals that this section describes refer to signal names that correspond to an AXI4 Lite interface. These signals adopt the prefix s<x>_axi4lite_.

Table 18.  AXI4 Lite Write Address (AW) command Channel
Port Name Width Direction Description
<prefix>_awaddr 44 Input Write Address. The write address gives the address of the first transfer in a write burst transaction.
<prefix>_awprot 3 Input

Protection Type [reserved for future use]. This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or an instruction access.

3’b0101 = No protection

<prefix>_awvalid 1 Input Write Address Valid. This signal indicates that the manager is signaling valid write address and control information.
<prefix>_awready 1 Output Write Address Ready. This signal indicates that the subordinate is ready to accept an address and associated control signals.
Table 19.  AXI4 Lite Write Data (W) Channel
Port Name Width Direction Description
<prefix>_wdata 32 Input Write Data.
<prefix>_wstrb 4 Input Write Strobes (Byte Enables). These signals indicate which bytes of the AXI4 Lite wdata signal hold valid data. There is one byte strobe for every eight bits of write data.
<prefix>_wvalid 1 Input Write Valid. This signal indicates that valid write data and write strobes are available.
<prefix>_wready 1 Output Write Ready. This signal indicates that the subordinate can accept write data.
Table 20.  AXI4 Lite Write Response (B) Channel
Port Name Width Direction Description
<prefix>_bresp 2 Output

Write Response. This signal indicates the status of the write transaction.

  • 2’b00 = OKAY; indicates that normal access is successful.
  • 2’b10 = SLVERR; an unsuccessful transaction.
  • 2'b11 = DECERR; indicates that the hard memory NoC could not extract a valid destination address from the address supplied in the original write command.
<prefix>_bvalid 1 Output Write Response Valid. This signal indicates that the host or manager is signaling a valid write response.
<prefix>_bready 1 Input Response Ready. This signal indicates that the manager can accept a write response.
Table 21.  AXI4 Lite Read Address (AR) command Channel
Port Name Width Direction Description
<prefix>_araddr 44 Input Read Address. The read address gives the address of the first transfer in a read burst transaction.
<prefix>_arprot 3 Input

Protection Type [reserved for future use]. This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or an instruction access.

3’b010 = No protection

<prefix>_arvalid 1 Input Read Address Valid. This signal indicates that the host or manager is signaling valid write address and control information.
<prefix>_arready 1 Output Read Address Ready. This signal indicates that the subordinate is ready to accept an address and associated control signals.
Table 22.  AXI4 Lite Read Data (R) Channel
Port Name Width Direction Description
<prefix>_rdata 32 Output Read Data.
<prefix>_rresp 2 Output

Read Response. This signal indicates the status of the read transfer:

  • 2’b00 = OKAY
  • 2’b10 = SLVERR: indicates an unsuccessful transaction.
  • 2'b11 = DECERR; indicates that the hard memory NoC could not extract a valid destination address from the address supplied in the original read command.
<prefix>_rvalid 1 Output Read Valid. This signal indicates that the subordinate is signaling the required read data.
<prefix>_rready 1 Input Read Ready. This signal indicates that the manager can accept the read data and response information.