Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 7/05/2023
Public

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8.1.2.1. NoC Initiator Intel FPGA IP AXI4/AXI4 Lite Interfaces

The interfaces that the NoC Initiator Intel FPGA IP can expose depend on the configuration that you select. You can expose the following interfaces:

Table 12.  Interfaces for NoC Initiator Intel FPGA IP
Interface Number Details
AXI4 0-23

These interfaces follow the AMBA AXI4 protocol specification. The NoC Initiator Intel FPGA IP exposes these interfaces when the Number of AXI4 interfaces is non-zero and the AXI4 Data Mode specifies equal read and write widths.

The Number of AXI4 interfaces parameter determines the number of AXI4 interfaces that you expose.

Each such interface uses the s<x>_axi4_ prefix for all signals, where x ranges from 0 to N-1, with N being the number of AXI4 interfaces.

AXI4 Read-only 0-23

These interfaces follow the AMBA AXI4 protocol specification but only include the AR and R channels. The NoC Initiator Intel FPGA IP exposes these interfaces when the Number of AXI4 interfaces is non-zero and the AXI4 Data Mode specifies unequal read and write widths.

The Number of AXI4 interfaces parameter determines the number of AXI4 read-only interfaces that you expose.

Each such interface uses the s<x>_ro_axi4_ prefix for all signals, where x ranges from 0 to N-1, with N being the number of AXI4 interfaces.

AXI4 Write-only 0-23

These interfaces follow the AMBA AXI4 protocol specification but only include the AW, W, and B channels. The NoC Initiator Intel FPGA IP exposes these interfaces when the Number of AXI4 interfaces is non-zero the AXI4 Data Mode specifies unequal read and write widths.

The Number of AXI4 interfaces parameter determines the number of write-only AXI4 interfaces that you expose.

Each such interface uses the s<x>_wo_axi4_ prefix for all its signals, where x ranges from 0 to N-1, with N being the number of AXI4 interfaces.

AXI4 Lite 0-4

These interfaces follow the AMBA AXI4 Lite protocol specification. The NoC Initiator Intel FPGA IP exposes these interfaces when the Number of AXI4 Lite interfaces is non-zero.

The Number of AXI4 Lite interfaces determines the number of AXI4 Lite interfaces that you expose.

Each such interface uses the s<x>_axi4lite_ prefix for all its signals, where x ranges from 0 to N-1, with N being the number of AXI4 Lite interfaces.