Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 7/05/2023

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Document Table of Contents

6.1. Adding NoC Connectivity and Address Mapping to the Simulation Netlist

The design netlist does not include NoC initiator-to-target connectivity and address-mapping, as Connecting NoC IP describes. To describe connectivity and address mapping for simulation, you create initiator-to-target-connections by registration function calls that you include in simulation startup code, for example in a Verilog initial block. Initiator simulation models provide the registration functions, and each call specifies the start address and address range of the connection to a specific target.

You can generate a registration include file for simulation after specifying the NoC connectivity and addressing. In the Intel® Quartus® Prime compilation flow, you specify these assignments in the NoC Assignment Editor, as Creating NoC Assignments for Compilation describes.

Alternatively, you can use an optional early RTL simulation flow where you specify these assignments in Platform Designer without the need to run Analysis & Elaboration, as NoC Design Flow Options describes.