Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 7/05/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.5.4. Transaction Ordering Support

The NoC subsystem is compliant with the AXI4 ordering model specification that is based on the use of the AxID AXI transaction identifier. Read transactions from the same NoC Initiator Intel FPGA IP that have the same ID complete in order, and similarly write transactions with the same ID complete in order. The AXI4 ordering model does not impose any order between reads and writes that have the same AXI ID. Transactions from the same NoC Initiator Intel FPGA IP that have different IDs have no reordering restriction.