Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 7/05/2023

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3.5.2. AXI4 Handshaking Support

Since the NoC initiators are located along the top and bottom edges of the die, timing closure on the valid and ready signals at the interface between user logic and the NoC Initiator Intel FPGA IP can be a challenge without pipelining registers within the NoC Initiator Intel FPGA IP. This IP offers two AXI handshake pipelining schemes. The default AXI4 handshaking scheme optimizes for interface frequency and includes pipeline registers. Alternatively, you can select low area handshaking logic that may have an Fmax penalty.

Both handshaking schemes are fully AXI compliant. The schemes only differ in their internal trade-off between area and frequency.