Intel® Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 5/22/2023

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4.5.2. Using the NoC Assignment Editor

The NoC Assignment Editor in the Intel® Quartus® Prime Pro Edition software allows you to make logical assignments for hard memory NoC-related blocks in your design. These assignments include grouping, connectivity, address mapping, and bandwidth requirements.

Note: Regardless of whether you instantiate the NoC IP using Platform Designer or directly in RTL, the netlist does not include the connections between NoC initiators, targets, and the clock control. You must specify these connections using the NoC Assignment Editor. Even if you specify NoC connections in Platform Designer for early RTL simulation, you must also use the NoC Assignment Editor to specify these connections prior to compilation. Refer to Options for Specifying NoC Connectivity and Addressing.
Figure 17. Network on Chip (NoC) Assignment Editor

After making assignments in the NoC Assignment Editor, you click Save to store the assignments in the Intel® Quartus® Prime settings file (.qsf). You must successfully complete Analysis & Elaboration before using the NoC Assignment Editor.

To access the NoC Assignment Editor, click Assignments > Network on Chip (NoC) Assignment Editor.

Specify assignments on the following NoC Assignment Editor tabs:

  • Group tab—specifies the Group Name of the NoC initiators and targets.
  • Connection tab—specifies the connections between NoC initiators and targets or SSM elements.
  • Attributes tab—specifies address mapping, bandwidth requirements, and transaction sizes for each connection.

The tabs appear in order of priority. The assignments made on the Group tab affect the assignments available in the Connection tab. The assignments made on the Connection tab affect the assignments available in the Attributes tab.

Complete the assignments on each tab in order before moving to the next tab.