Intel® Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 5/22/2023

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Document Table of Contents

4.3. NoC Building Blocks

Creating a hard memory NoC design involves the following building blocks that you configure using corresponding Intel FPGA IP:

  • NoC Initiators—configure using the NoC Initiator Intel FPGA IP.
  • NoC Targets—configured by the High Bandwidth Memory (HBM2E) Interface Intel® Agilex® 7 FPGA IP and External Memory Interfaces (EMIF) IP.
  • NoC Clock Control—configure the NoC PLL and NoC SSM using the NoC Clock Control Intel FPGA IP.