Intel® Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 5/22/2023

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6.4. Contents of Simulation Registration Include File

Generate HDL generates the simulation registration include file in your project directory, in Verilog HDL format, with the name <top_module> This simulation registration include file has all the necessary registration information for each initiator-to-target connection using a SIM_TOP_PATH macro to specify the hierarchical path.

Note: This file is only available in Verilog HDL format. If your design uses VHDL, you must create a top-level wrapper in Verilog HDL to use this registration include file and perform a mixed-language simulation.

To use this file, edit your top-level simulation testbench to define the SIM_TOP_PATH macro to complete the hierarchical path to the initiators and targets relative to the testbench.

Once you define the SIM_TOP_PATH macro, use the `include directive to include this file into your simulation testbench and apply the registration statements. If your simulation environment instantiates these modules at multiple places in your hierarchy, redefine the SIM_TOP_PATH macro and re-include this file for each additional instantiation. Do not edit the simulation registration include file directly because the Compiler rewrites this file during each compilation.

The format for the registration statements in Verilog HDL is as follows. Use the Verilog HDL hierarchy delimiter, ., instead of the Intel® Quartus® Prime hierarchy delimiter, |. Also, express hexadecimal numbers using Verilog HDL format.

<hierarchical initiator path name>.register_if\
   (<hierarchical target path name>.get_if(),\
   <hexadecimal base address>, \
     <hexadecimal span of memory>);

For example, the following registration statement specifies a connection with a base address of 0 and spanning 40000000 (hexadecimal) addresses:

.get_if(),0X00000000000, 40'h40000000);
Figure 31. Example Contents of Simulation Registration Include File Generation