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1. Answers to Top FAQs
2. Network-on-Chip (NoC) Overview
3. Hard Memory NoC in Intel® Agilex® 7 M-Series FPGAs
4. NoC Design Flow in Intel® Quartus® Prime Pro Edition
5. NoC Real-time Performance Monitoring
6. Simulating NoC Designs
7. NoC Power Estimation
8. Hard Memory NoC IP Reference
9. Document Revision History of Intel® Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide
6.1. Adding NoC Connectivity and Address Mapping to the Simulation Netlist
6.2. Generating a Simulation Registration Include File ( Intel® Quartus® Prime Compilation Flow)
6.3. Generating a Simulation Registration Include File (Optional Early RTL Simulation Flow)
6.4. Contents of Simulation Registration Include File
8.1.2.1. NoC Initiator Intel FPGA IP AXI4/AXI4 Lite Interfaces
8.1.2.2. NoC Initiator AXI4 User Interface Signals
8.1.2.3. NoC Initiator Intel FPGA IP AXI4 Lite User Interface Signals
8.1.2.4. NoC Initiator Intel FPGA IP Clock and Reset Signals
8.1.2.5. NoC Initiator Intel FPGA IP Platform Designer-Only Signals
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8.2.2. NoC Clock Control Intel FPGA IP Interfaces
Interfaces for NoC Clock Control FPGA IP describes the interfaces on the NoC Clock Control Intel FPGA IP. There are no RTL connections between the NoC Clock Control Intel FPGA IP and the hard memory NoC. Rather, you specify these connections using assignments in the NoC Assignment Editor, as Making NoC Assignments describes.
Port Name | Width | Direction | Description |
---|---|---|---|
refclk | 1 | Input | Reference clock for NoC PLL |
pll_lock_o | 1 | Output | Lock signal for NoC PLL |