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1. Answers to Top FAQs
2. Network-on-Chip (NoC) Overview
3. Hard Memory NoC in Intel® Agilex® 7 M-Series FPGAs
4. NoC Design Flow in Intel® Quartus® Prime Pro Edition
5. NoC Real-time Performance Monitoring
6. Simulating NoC Designs
7. NoC Power Estimation
8. Hard Memory NoC IP Reference
9. Document Revision History of Intel® Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide
6.1. Adding NoC Connectivity and Address Mapping to the Simulation Netlist
6.2. Generating a Simulation Registration Include File ( Intel® Quartus® Prime Compilation Flow)
6.3. Generating a Simulation Registration Include File (Optional Early RTL Simulation Flow)
6.4. Contents of Simulation Registration Include File
8.1.2.1. NoC Initiator Intel FPGA IP AXI4/AXI4 Lite Interfaces
8.1.2.2. NoC Initiator AXI4 User Interface Signals
8.1.2.3. NoC Initiator Intel FPGA IP AXI4 Lite User Interface Signals
8.1.2.4. NoC Initiator Intel FPGA IP Clock and Reset Signals
8.1.2.5. NoC Initiator Intel FPGA IP Platform Designer-Only Signals
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3.2.2. GPIO-B Segments
GPIO-B segments are NoC segments that interface with GPIO-B blocks, span one FPGA clock sector, and consist of the following:
- Three AXI4 initiators on the FPGA fabric side.
- Two AXI4 targets on the GPIO-B block side.
- One AXI4 Lite target on the GPIO-B block side.
- A network of switches that transfer packets laterally along the hard memory NoC and connect to the AXI4 initiators and targets.
Figure 4. GPIO-B Segments
Note: There is an additional service network running parallel to the main switch network. This service network connects the NoC SSM to the AXI4 Lite initiators and targets. NoC initiators can send transactions over the main network to the NoC SSM to access the service network for sideband configuration and system monitoring. Figure 4. GPIO-B Segments does not show this service network.