Intel® Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 5/22/2023

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Document Table of Contents

4.4.2. Connecting NoC IP

The following procedures describe connecting NoC IP in either Platform Designer or in your design RTL.

Making NoC Connections in Platform Designer

  1. If your design instantiates NoC IP generated with Platform Designer, connect the NoC IP to external pins or FPGA core logic, as appropriate for your application, in the System View tab of Platform Designer.
  2. (Optional) To enable early RTL simulation after generating HDL in Platform Designer, without running Analysis & Elaboration, perform the following steps. If you do not want early RTL simulation, proceed to step 3.
    1. On the Platform Designer System View tab, connect the AXI4 NoC manager ports to appropriate AXI4 NoC subordinate ports or to AXI4-Lite NOC subordinate ports. The AXI4 NoC manager ports are on the NoC Initiator Intel FPGA IP. The AXI4 NoC subordinate ports or AXI4-Lite NOC subordinate ports are on the High Bandwidth Memory (HBM2E) Interface Intel® Agilex® 7 FPGA IP and on the External Memory Interfaces (EMIF) IP.
    2. On the Platform Designer Address Map tab, assign starting addresses for each NoC initiator to target connection. If an initiator connects to multiple targets, ensure that each target has a unique starting address.
      Note: For NoC connections, you only need to specify the starting address. Specifying the ending address for NoC connections is unnecessary.
    3. For all non-NoC system connections, specify the start and ending addresses on the Address Map tab.
  3. Save your Platform Designer system and click Generate HDL.
  4. If you completed optional step 2, the design is now ready for early RTL simulation. Otherwise, click Processing > Start > Start Analysis & Elaboration.
  5. Define NoC connectivity and addressing in the NoC Assignment Editor to prepare your design for RTL simulation, as Making NoC Assignments describes.

Making NoC Connections in RTL

If your design instantiates NoC IP directly in RTL, connect these IP to external pins or FPGA core logic in your design RTL, as appropriate for your application.

Note: The early RTL simulation option is not available when using RTL entry for NoC IP. The AXI4 NoC manager and AXI4 NoC subordinate ports described in the Platform Designer Entry section above do not exist in the RTL representations of these IP. Run Analysis & Elaboration and define NoC connectivity and addressing in the NoC Assignment Editor to prepare your design for RTL simulation.
Note: Regardless of whether you instantiate the NoC IP using Platform Designer or directly in RTL, the netlist does not include the connections between NoC initiators, targets, and the clock control. You must specify these connections using the NoC Assignment Editor. Even if you specify NoC connections in Platform Designer for early RTL simulation, you must still use the NoC Assignment Editor to specify these connections prior to compilation.