Intel® Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 5/22/2023

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4.5.1. Creating NoC Assignments for Compilation

After instantiating NoC-related IP in your design, connecting initiators to AXI4 managers, and connecting other NoC IP to external ports, you next run Intel® Quartus® Prime Analysis & Elaboration on your design. Analysis & Elaboration reads your design, discovers the hard memory NoC-related IP in your design, and determines the location of the IP in the design hierarchy.

After Analysis & Elaboration is complete, you use the NoC Assignment Editor to make logical assignments for the NoC-related IP in your design, including the following:

  • Assign the NoC-related IP into one of two groups: one group for each edge of the die where you use the hard memory NoC. If you only use the hard memory NoC along one edge of the die, then all NoC IP in the design would belong to the same group.
  • Assign connections between initiators and targets.
  • Assign address mapping for connections between initiators and targets.
  • Specify the read and write bandwidth and transaction size between connected initiators and targets.

For details about using the NoC Assignment Editor, refer to Using the NoC Assignment Editor

To run a simulation at this point in the flow, after creating logical assignments, you must re-run Analysis & Elaboration to generate the simulation registration file that communicates connection and address mapping to your simulation environment. For simulation flow details, refer to Simulating NoC Designs.

To proceed to compilation, run Analysis & Synthesis to prepare your design for physical assignments. You can optionally use the Intel® Quartus® Prime Interface Planner to assign locations for hard memory NoC initiator, target, PLL, and SSM blocks, and make assignments for other I/O-related IP, as Step 5: Make Physical Assignments Using Interface Planner describes.