Intel® Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

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ID 768844
Date 5/22/2023
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Network-on-Chip (NoC) Overview 3. Hard Memory NoC in Intel® Agilex® 7 M-Series FPGAs 4. NoC Design Flow in Intel® Quartus® Prime Pro Edition 5. NoC Real-time Performance Monitoring 6. Simulating NoC Designs 7. NoC Power Estimation 8. Hard Memory NoC IP Reference 9. Document Revision History of Intel® Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide
2. Network-on-Chip (NoC) Overview x
2.1. Introduction to Intel® Agilex® 7 M-Series FPGAs 2.2. Terminology for Intel® Agilex® 7 M-Series FPGAs 2.3. General NoC Architecture and Applications
2.3. General NoC Architecture and Applications x
2.3.1. General NoC Architecture 2.3.2. Example NoC Applications
2.3.2. Example NoC Applications x
2.3.2.1. Parallel Computing NoC Application 2.3.2.2. SmartNIC NoC Application
3. Hard Memory NoC in Intel® Agilex® 7 M-Series FPGAs x
3.1. High-Level Architecture 3.2. NoC Segments 3.3. Fabric NoC 3.4. NoC Protocol Support 3.5. NoC Design Considerations
3.2. NoC Segments x
3.2.1. UIB Segments 3.2.2. GPIO-B Segments 3.2.3. GPIO-B and HPS Segment 3.2.4. SDM Segment 3.2.5. PLL and SSM Segment
3.4. NoC Protocol Support x
3.4.1. AXI4 Protocol Support 3.4.2. AXI4 Handshaking Support 3.4.3. Quality of Service (QoS) Support 3.4.4. Transaction Ordering Support 3.4.5. AXI4 Lite Protocol Support
3.5. NoC Design Considerations x
3.5.1. Determining the Number of NoC Targets 3.5.2. Determining the Number of NoC Initiators 3.5.3. Fabric NoC Considerations 3.5.4. Latency Considerations 3.5.5. Initiator and Target Bandwidth Considerations 3.5.6. Horizontal Bandwidth Considerations 3.5.7. GPIO-B Bypass Mode and Initiators
4. NoC Design Flow in Intel® Quartus® Prime Pro Edition x
4.1. Hard Memory NoC Design Flow Overview 4.2. Using NoC Example Designs 4.3. NoC Building Blocks 4.4. Connecting NoC IP 4.5. Making NoC Logical Assignments 4.6. (Recommended) Make NoC Physical Assignments Using Interface Planner 4.7. Compiling the NoC Design
4.1. Hard Memory NoC Design Flow Overview x
4.1.1. Options for Specifying NoC Connectivity and Addressing
4.3. NoC Building Blocks x
4.3.1. NoC Initiators 4.3.2. NoC Targets 4.3.3. NoC Clock Control
4.4. Connecting NoC IP x
4.4.1. General NoC IP Connectivity Guidelines 4.4.2. Connecting NoC IP 4.4.3. NoC Initiator Connectivity Guidelines 4.4.4. NoC Target Connectivity Guidelines 4.4.5. NoC Clock Control Connectivity Guidelines
4.5. Making NoC Logical Assignments x
4.5.1. Creating NoC Assignments for Compilation 4.5.2. Using the NoC Assignment Editor
4.5.2. Using the NoC Assignment Editor x
4.5.2.1. Step 1: Make Group Assignments in the NoC Assignment Editor 4.5.2.2. Step 2: Make Connection Assignments in the NoC Assignment Editor 4.5.2.3. Step 3: Make Attribute Assignments in the NoC Assignment Editor 4.5.2.4. Step 4: Validate Logical NoC Assignments and Generate Simulation File
4.6. (Recommended) Make NoC Physical Assignments Using Interface Planner x
4.6.1. Using Interface Planner 4.6.2. Recommended Placement Order for NoC Elements in Interface Planner 4.6.3. Hard Memory NoC Locations in Interface Planner 4.6.4. NoC Performance Reports in Interface Planner
4.7. Compiling the NoC Design x
4.7.1. Fitter NoC Reports 4.7.2. Viewing NoC Elements in Chip Planner
6. Simulating NoC Designs x
6.1. Adding NoC Connectivity and Address Mapping to the Simulation Netlist 6.2. Generating a Simulation Registration Include File ( Intel® Quartus® Prime Compilation Flow) 6.3. Generating a Simulation Registration Include File (Optional Early RTL Simulation Flow) 6.4. Contents of Simulation Registration Include File
7. NoC Power Estimation x
7.1. Using the Intel FPGA PTC to Estimate NoC Power
8. Hard Memory NoC IP Reference x
8.1. NoC Initiator Intel FPGA IP 8.2. NoC Clock Control Intel FPGA IP
8.1. NoC Initiator Intel FPGA IP x
8.1.1. NoC Initiator Intel FPGA IP Parameters 8.1.2. NoC Initiator Intel FPGA IP Interfaces
8.1.2. NoC Initiator Intel FPGA IP Interfaces x
8.1.2.1. NoC Initiator Intel FPGA IP AXI4/AXI4 Lite Interfaces 8.1.2.2. NoC Initiator AXI4 User Interface Signals 8.1.2.3. NoC Initiator Intel FPGA IP AXI4 Lite User Interface Signals 8.1.2.4. NoC Initiator Intel FPGA IP Clock and Reset Signals 8.1.2.5. NoC Initiator Intel FPGA IP Platform Designer-Only Signals
8.2. NoC Clock Control Intel FPGA IP x
8.2.1. NoC Clock Control Intel FPGA IP Parameters 8.2.2. NoC Clock Control Intel FPGA IP Interfaces 8.2.3. NoC Clock Control Intel FPGA IP Platform Designer-only Signals
1. Answers to Top FAQs
2. Network-on-Chip (NoC) Overview
3. Hard Memory NoC in Intel® Agilex® 7 M-Series FPGAs
4. NoC Design Flow in Intel® Quartus® Prime Pro Edition
5. NoC Real-time Performance Monitoring
6. Simulating NoC Designs
7. NoC Power Estimation
8. Hard Memory NoC IP Reference
9. Document Revision History of Intel® Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

3.2.4. SDM Segment

The hard memory NoC on the bottom edge of the device also has a segment that spans the Secure Device Manager (SDM). There is no connection between the SDM and the hard memory NoC, and all signals from the SDM bypass the hard memory NoC. This NoC segment spans one clock sector and consists of the following:

  • One AXI4 initiator on the FPGA fabric side.
  • A switch that transfers packets laterally along the hard memory NoC and connects to the AXI4 initiator.
Figure 6. NoC SDM Segment


Note: There is an additional service network running parallel to the main switch network. This service network connects the NoC SSM to the AXI4 Lite initiators and targets. NoC initiators can send transactions over the main network to the NoC SSM to access the service network for sideband configuration and system monitoring. Figure 6. NoC SDM Segment does not show this network.
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