Intel® Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 5/22/2023
Public

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8.2. NoC Clock Control Intel FPGA IP

You use the NoC Clock Control Intel FPGA IP to insert the NoC PLL and NoC SSM. One NoC Clock Control Intel FPGA IP instance is required for the hard memory NoC running along the top edge of the die. A second NoC Clock Control Intel FPGA IP instance is required for the hard memory NoC along the bottom of the die.

Access the NoC Clock Control Intel FPGA IP in the IP Catalog by expanding the Intel FPGA Interconnect category and then expanding the NoC subcategory.