Intel® Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 5/22/2023

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Document Table of Contents

4.1. Hard Memory NoC Design Flow Overview

Creating a hard memory NoC design in the Intel® Quartus® Prime software consists of the following high level steps that this chapter describes in detail:

Figure 15. Hard Memory NoC Design Flow

  1. Instantiate NoC-related IP, including the NoC Initiator Intel FPGA IP, the HBM2E IP or external memory IP that contain the NoC targets, and the NoC Clock Control Intel FPGA IP in your design using Platform Designer or directly in design RTL.
    Note: If you enter NoC connectivity and addressing in Platform Designer, you can use an optional early simulation flow, as Options for Specifying NoC Connectivity and Addressing describes.
  2. Run Intel® Quartus® Prime Analysis & Elaboration (Processing > Start > Start Analysis & Elaboration).
  3. Define logical constraints for NoC connectivity, addressing, and performance targets in the NoC Assignment Editor, as Making NoC Logical Assignments describes.
    Note: If you define NoC connectivity and addressing in Platform Designer, you must also define the same exact NoC groups, connectivity, and addressing in the NoC Assignment Editor before Intel® Quartus® Prime compilation.
  4. (Optional) Rerun Analysis & Elaboration and perform RTL simulation of the NoC design, as Simulating NoC Designs describes.
  5. (Recommended) Run Analysis & Synthesis and then assign physical locations for NoC elements and other periphery elements, as Step 5: Make Physical Assignments Using Interface Planner describes. Otherwise, the Intel® Quartus® Prime Fitter makes the physical assignments during design compilation.
  6. Compile your design and review the placement and performance reports, as Compiling the NoC Design describes.