F-Tile 25G Ethernet Intel® FPGA IP Design Example User Guide

ID 750200
Date 11/29/2023
Public
Document Table of Contents
Give Feedback

2.4.1. Testbench

Figure 6. Block Diagram of the F-Tile 25G Ethernet Single-Channel Design Example Simulation Testbench
Table 5.  Testbench Components
Component Description
Device under test (DUT) The F-Tile 25G Ethernet Intel FPGA IP core.
Ethernet Packet Generator and Packet Monitor
  • Packet generator generates frames and transmit to the DUT.
  • Packet Monitor monitors TX and RX datapaths and displays the frames in the simulator console.
F-Tile Reference and System PLL Clocks Intel® FPGA IP Generates transceiver and system PLL reference clocks.