F-Tile 25G Ethernet Intel® FPGA IP Design Example User Guide

ID 750200
Date 11/29/2023
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3.4.3. Test Case—Single-Channel Design Example with Dynamic Reconfiguration

The simulation test case performs the following actions:

  1. Instantiates F-Tile 25G Ethernet Intel® FPGA IP, dynamic reconfiguration controller, and SYS PLL.
  2. Starts up the design example with an operation speed of 25G.
  3. Waits for RX clock and RX alignment to settle.
  4. Transmits and receives 10 valid 64-bit data on 25G speed.
  5. The testbench performs the dynamic reconfiguration operation to switch the speed to 10G.
  6. Waits for RX clock and RX alignment to settle.
  7. Transmits and receives 10 valid 64-bit data on 10G speed.
  8. The testbench performs the dynamic reconfiguration operation to switch the speed back to 25G.
  9. Waits for RX clock and RX alignment to settle.
  10. Transmits and receives 10 valid 64-bit data on 25G speed.
  11. The successful testbench displays "Testbench complete.".
The following sample output illustrates a successful simulation test run: