F-Tile 25G Ethernet Intel® FPGA IP Design Example User Guide

ID 750200
Date 11/29/2023
Public
Document Table of Contents
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3. F-Tile 25G Ethernet Single Channel Design Example with Dynamic Reconfiguration

The F-Tile 25G Ethernet single-channel design example with dynamic reconfiguration demonstrates an Ethernet solution for Intel Agilex® 7 devices using the F-Tile 25G Ethernet Intel FPGA IP core.

Generate the design example from the Example Design tab of the F-Tile 25G Ethernet Intel FPGA IP parameter editor. You can also choose to generate the design with or without the Reed-Solomon Forward Error Correction (RS-FEC) feature.