F-Tile 25G Ethernet Intel® FPGA IP Design Example User Guide

ID 750200
Date 11/29/2023
Document Table of Contents

3.3.1. Design Components

Table 8.  Design Components
Component Description
F-Tile 25G Ethernet Intel FPGA IP

Consists of MAC, PCS, and Transceiver PHY, with the following configuration:

  • Core Variant: MAC+PCS+PMA
  • Enable flow control: Optional
  • Enable link fault generation: Optional
  • Enable preamble passthrough: Optional
  • Enable statistics collection: Optional
  • Enable MAC statistics counters: Optional
  • Enable Native PHY Debug Master Endpoint (NPDME): Optional
  • Reference clock frequency: 156.25
SYS PLL Generates reference and system clocks for the 10G/25G transceivers.
Client logic Consists of:
  • Traffic generator, which generates burst packets to the F-Tile 25G Ethernet Intel FPGA IP core for transmission.
  • Traffic monitor, which monitors burst packets that are coming from the F-Tile 25G Ethernet Intel FPGA IP core.
Source and Probe Source and probe signals, including system reset input signal, which you can use for debugging.
Dynamic reconfiguration controller Dynamic reconfiguration controller is generated when you generate the single-channel design example with dynamic reconfiguration.