F-Tile 25G Ethernet Intel® FPGA IP Design Example User Guide

ID 750200
Date 11/29/2023
Document Table of Contents

3.3. Functional Description

The F-Tile 25G Ethernet single-channel design example with dynamic reconfiguration consists of MAC+PCS+PMA core variant. The following block diagrams show the design components and the top-level signals of the MAC+PCS+PMA core variant in the F-Tile 25G Ethernet design example.

Figure 8. Block Diagram—F-Tile 25G Ethernet Single-Channel Design Example with Dynamic Reconfiguration (MAC+PCS+PMA Core Variant)