F-Tile 25G Ethernet Intel® FPGA IP Design Example User Guide

ID 750200
Date 11/29/2023
Public
Document Table of Contents
Give Feedback

1.3. Generating Tile Files

The Support-Logic Generation is a pre-synthesis step used to generate tile-related files required for simulation and hardware design. The tile generation is required for all F-Tile based design simulations. You must complete this step before the simulation.

  1. At the command prompt, navigate to the compilation_test_design folder in your example design: cd <your_design_path>/compilation_test_design.
  2. Run the following command: quartus_tlg alt_eth_25g