F-Tile 25G Ethernet Intel® FPGA IP Design Example User Guide

ID 750200
Date 11/29/2023
Document Table of Contents

3.4.1. Testbench

Figure 9. Block Diagram of the F-Tile 25G Ethernet Single-Channel Design Example with Dynamic Reconfiguration Simulation Testbench
Table 9.  Testbench Components
Component Description
Device under test (DUT) The F-Tile 25G Ethernet Intel FPGA IP core.
Ethernet Packet Generator and Packet Monitor
  • Packet generator generates frames and transmit to the DUT.
  • Packet Monitor monitors TX and RX datapaths and displays the frames in the simulator console.
SYS PLL Generates clock for the Intel Agilex® 7 I-Series SoC 25G transceiver which is wrapped in the F-Tile 25G Ethernet Intel FPGA IP.
Dynamic reconfiguration controller If you generate the single-channel design example with dynamic reconfiguration, this IP is automatically instantiated.