F-Tile 25G Ethernet Intel® FPGA IP Design Example User Guide

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ID 750200
Date 6/26/2023
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. F-Tile 25G Ethernet Design Example for Intel Agilex® 7 Devices 3. F-Tile 25G Ethernet Intel FPGA IP Design Example User Guide Archives 4. Document Revision History for F-Tile 25G Ethernet Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Generating Tile Files 1.4. Simulating the 25G Ethernet Intel FPGA IP Design Example Testbench 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the 25G Ethernet Intel FPGA IP Hardware Design Example
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
2. F-Tile 25G Ethernet Design Example for Intel Agilex® 7 Devices x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Compilation 2.6. Hardware Testing
2.3. Functional Description x
2.3.1. Design Components
2.4. Simulation x
2.4.1. Testbench 2.4.2. Simulation Design Example Components 2.4.3. Test Case
2.6. Hardware Testing x
2.6.1. Test Procedure
1. Quick Start Guide
2. F-Tile 25G Ethernet Design Example for Intel Agilex® 7 Devices
3. F-Tile 25G Ethernet Intel FPGA IP Design Example User Guide Archives
4. Document Revision History for F-Tile 25G Ethernet Intel® FPGA IP Design Example User Guide

4. Document Revision History for F-Tile 25G Ethernet Intel® FPGA IP Design Example User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2023.06.26 23.2 2.0.0
  • Updated steps in Simulating the F-Tile 25G Ethernet Intel FPGA Design Example Testbench topic.
  • Updated steps in Test Procedure topic.
  • Updated product family name to "Intel Agilex® 7"
2022.10.14 22.3 1.0.0 Initial release.
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