F-Tile 25G Ethernet Intel® FPGA IP Design Example User Guide

ID 750200
Date 11/29/2023
Document Table of Contents

2. F-Tile 25G Ethernet Design Example for Intel Agilex® 7 Devices

The F-Tile 25G Ethernet design example demonstrates an Ethernet solution for Intel Agilex® 7 devices using the 25G Ethernet Intel FPGA IP core.

Generate the design example from the Example Design tab of the 25G Ethernet Intel FPGA IP parameter editor. You can also choose to generate the design with or without the Reed-Solomon Forward Error Correction (RS-FEC) feature.