F-Tile Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 741328
Date 4/03/2023

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Document Table of Contents TBI Interface Signals

If the core variation does not include an embedded PMA, the PCS block provides a 125-MHz ten-bit interface (TBI) to an external SERDES chip.
Table 65.  TBI Interface Signals for External SERDES Chip
Name I/O Description
tbi_tx_d[9:0] O TBI transmit data. The PCS function transmits data on this bus synchronous to tbi_tx_clk.
tbi_tx_clk I 125-MHz TBI transmit clock from external SERDES, typically sourced by the local reference clock oscillator.
tbi_rx_clk I 125-MHz TBI receive clock from external SERDES, typically sourced by the line clock recovered from the encoded line stream.
tbi_rx_d[9:0] I TBI receive data. This bus carries the data from the external SERDES. Synchronize the bus with tbi_rx_clk. The data can be arbitrary aligned.