F-Tile Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 741328
Date 4/03/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents Deterministic Latency Clock Signals

Table 74.  Deterministic Latency Clock Signals
Name I/O Width Description
i_dl_sampling_clk I 1 Sampling clock for deterministic latency logic. The default frequency value is 228.571429 MHz.