F-Tile Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 741328
Date 4/03/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2. About This IP

The F-tile Triple-Speed Ethernet Intel® FPGA IP is a configurable intellectual property (IP) core that complies with the IEEE 802.3 standard.

It incorporates a 10/100/1000 Mbps Ethernet media access controller (MAC) and an optional 1000BASE-X/SGMII physical coding sublayer (PCS) with an embedded physical medium attachment (PMA) built with either on-chip transceiver I/Os or LVDS I/Os. When offered in MAC-only mode, the IP connects with an external PHY chip using Media Independent Interface (MII), Gigabit Media Independent Interface (GMII), or Reduced Gigabit Media Independent Interface (RGMII).