F-Tile Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 741328
Date 4/03/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

9.2. Recommended Clock Frequency

Table 103.  Recommended Clock Input Frequency For Each IP Variant
IP Variant Clock Recommended Frequency (MHz)
10/100/1000-Mbps Ethernet MAC (with Internal FIFO buffers) CLK 50–125
TX_CLK 125
RX_CLK 125
FF_TX_CLK
  • For 32 bits FIFO: 100
  • For 8 bits FIFO: 125
FF_RX_CLK
  • For 32 bits FIFO: 100
  • For 8 bits FIFO: 125
10/100/1000-Mbps Ethernet MAC (without Internal FIFO buffers) CLK 50–125
TX_CLK <N> 125
RX_CLK <N> 125
RX_AFULL_CLK 100
10/100/1000-Mbps Ethernet MAC with 1000BASE-X/SGMII PCS (with Internal FIFO buffers) CLK 50–125
FF_TX_CLK
  • For 32 bits FIFO: 100
  • For 8 bits FIFO: 125
FF_RX_CLK
  • For 32 bits FIFO: 100
  • For 8 bits FIFO: 125
TBI_TX_CLK 125
TBI_RX_CLK 125
REF_CLK 125
10/100/1000-Mbps Ethernet MAC with 1000BASE-X/SGMII PCS (without Internal FIFO buffers) CLK 50–125
RX_AFULL_CLK 100
TBI_TX_CLK <N> 125
TBI_RX_CLK <N> 125
REF_CLK 125
1000BASE-X/SGMII PCS only REG_CLK 50–125
REF_CLK 125
TBI_TX_CLK 125
TBI_RX_CLK 125
10/100/1000 Ethernet MAC with 1000BASE-X/SGMII 2XTBI (with Internal FIFO buffers) CLK 50–125
TX_CLK_125 125
RX_CLK_125 125
FF_TX_CLK
  • For 32 bits FIFO: 100
  • For 8 bits FIFO: 125
FF_RX_CLK
  • For 32 bits FIFO: 100
  • For 8 bits FIFO: 125
TX_CLK_62_5 62.5
RX_CLK_62_5 62.5
PLL_REFCLK0 156.25
1000BASE-X/SGMII 2XTBI PCS only REG_CLK 50–125
TX_CLK_125 125
RX_CLK_125 125
TX_CLK_62_5 62.5
RX_CLK_62_5 62.5
TBI2X_TX_CLK 62.5
TBI2X_RX_CLK 62.5