F-Tile Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 741328
Date 4/03/2023

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6.2. PCS Configuration Register Space

This section describes the PCS registers. Use the registers to configure the PCS function or retrieve its status.
Note: In MAC and PCS variations, the PCS registers occupy the MAC register space and you access these registers via the MAC 32-bit Avalon memory-mapped control interface. PCS registers are 16 bits wide, they therefore occupy only the lower 16 bits and the upper 16 bits are set to 0. The offset of the first PCS register in this variation is mapped to dword offset 0x80.

If you instantiate the IP using the IP Catalog flow, use word addressing to access the register spaces. When you instantiate MAC and PCS variations, map the PCS registers to the respective dword offsets in the MAC register space by adding the PCS word offset to the offset of the first PCS. For example,

  • In the PCS only variation, you can access the if_mode register at word offset 0x14.
  • In the fMAC and PCS variations, map the if_mode register to the MAC register space:
    • Offset of the first PCS register = 0x80
    • if_mode word offset = 0x14
    • if_mode dword offset = 0x80 + 0x14 = 0x94

If you instantiate the MAC and PCS variation using the Platform Designer system, access the register spaces using byte addressing. Convert the dword offsets to byte offsets by multiplying the dword offsets by 4. For example,

  • For MAC registers:
    • comand_config dword offset = 0x02
    • comand_config byte offset = 0x02 × 4 = 0x08
  • For PCS registers, map the registers to the dword offsets in the MAC register space before you convert the dword offsets to byte offsets:
    • if_mode word offset = 0x14
    • if_mode dword offset = 0x80 + 0x14 = 0x94
    • if_mode byte offset = 0x94 × 4 = 0x250
Table 38.  PCS Configuration Registers


Register Name R/W Description HW Reset
0x00 control RW PCS control register. Use this register to control and configure the PCS function. 0x1140
0x01 status RO Status register. Provides information on the operation of the PCS function. 0x0089
0x02 phy_identifier RO 32-bit PHY identification register. This register is set to the value of the PHY ID parameter. Bits 31:16 are written to word offset 0x02. Bits 15:0 are written to word offset 0x03. 0x0101
0x03 0x0101
0x04 dev_ability RW Use this register to advertise the device abilities to a link partner during auto-negotiation. In SGMII MAC mode, the PHY does not use this register during auto-negotiation. 0x01A0
0x05 partner_ability RO Contains the device abilities advertised by the link partner during auto-negotiation. 0x0000
0x06 an_expansion RO Auto-negotiation expansion register. Contains the PCS function capability and auto-negotiation status. 0x0000
0x07 device_next_page RO The PCS function does not support these features. These registers are always set to 0x0000 and any write access to the registers is ignored. 0x0000
0x08 partner_next_page 0x0000
0x09 master_slave_cntl 0x0000
0x0A master_slave_stat 0x0000
0x0B – 0x0E Reserved
0x0F extended_status RO The PCS function does not implement extended status registers.
Specific Extended Registers
0x10 scratch RW Scratch register. Provides a memory location to test register read and write operations. 0x0000
0x11 rev RO The PCS function revision. Always set to the current version of the IP. <IP version number>
0x12 link_timer RW 21-bit auto-negotiation link timer. Set the link timer value from 0 to 16 ms in 8 ns steps (125 MHz clock periods). The reset value sets the link timer to 10 ms.
  • Bits 15:0 are written to word offset 0x12. Bit 0 of word offset 0x12 is always set to 0, thus any value written to it is ignored.
  • Bits 20:16 are written to word offset 0x13. The remaining bits are reserved and always set to 0.
0x13 0x0009
0x14 if_mode RW Interface mode. Use this register to specify the operating mode of the PCS function; 1000BASE-X or SGMII. 0
0x17 – 0x1F Reserved 0