Visible to Intel only — GUID: bhc1410931508020
Ixiasoft
1. About the F-Tile Triple Speed Ethernet Intel FPGA IP User Guide
2. About This IP
3. Getting Started
4. Parameter Settings
5. Functional Description
6. Configuration Register Space
7. Interface Signals
8. Design Considerations
9. Timing Constraints
10. Software Programming Interface
11. F-Tile Triple-Speed Ethernet Intel® FPGA IP User Guide Archives
12. Document Revision History for the F-tile Triple-Speed Ethernet Intel® FPGA IP User Guide
A. Ethernet Frame Format
B. Simulation Parameters
5.1.1. MAC Architecture
5.1.2. MAC Interfaces
5.1.3. MAC Transmit Datapath
5.1.4. MAC Receive Datapath
5.1.5. MAC Transmit and Receive Latencies
5.1.6. FIFO Buffer Thresholds
5.1.7. Congestion and Flow Control
5.1.8. Magic Packets
5.1.9. MAC Local Loopback
5.1.10. MAC Reset
5.1.11. PHY Management (MDIO)
5.1.12. Connecting MAC to External PHYs
6.1.1. Base Configuration Registers (Dword Offset 0x00 – 0x17)
6.1.2. Statistics Counters (Dword Offset 0x18 – 0x38)
6.1.3. Transmit and Receive Command Registers (Dword Offset 0x3A – 0x3B)
6.1.4. Supplementary Address (Dword Offset 0xC0 – 0xC7)
6.1.5. IEEE 1588v2 Feature (Dword Offset 0xD0 – 0xD6)
6.1.6. Deterministic Latency (Dword Offset 0xE1– 0xE3)
6.1.7. IEEE 1588v2 Feature PMA Delay
7.1.1. 10/100/1000 Ethernet MAC Signals
7.1.2. 10/100/1000 Multiport Ethernet MAC Signals
7.1.3. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS Signals
7.1.4. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS and Embedded PMA Signals (F-Tile)
7.1.5. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with 1000BASE-X/SGMII 2XTBI PCS Signals
7.1.6. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with IEEE 1588v2 , 1000BASE-X/SGMII 2XTBI PCS, and Embedded Serial PMA Signals
7.1.7. 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS Signals
7.1.8. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA Signals
7.1.9. 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA Signals
7.1.10. 1000BASE-X/SGMII PCS Signals
7.1.11. 1000BASE-X/SGMII 2XTBI PCS Signals
7.1.12. 1000BASE-X/SGMII PCS and PMA Signals
7.1.1.1. Clock and Reset Signals
7.1.1.2. Clock Enabler Signals
7.1.1.3. MAC Control Interface Signals
7.1.1.4. MAC Status Signals
7.1.1.5. MAC Receive Interface Signals
7.1.1.6. MAC Transmit Interface Signals
7.1.1.7. Pause and Magic Packet Signals
7.1.1.8. MII/GMII/RGMII Signals
7.1.1.9. PHY Management Signals
7.1.1.10. ECC Status Signals
10.6.1. alt_tse_mac_get_common_speed()
10.6.2. alt_tse_mac_set_common_speed()
10.6.3. alt_tse_phy_add_profile()
10.6.4. alt_tse_system_add_sys()
10.6.5. triple_speed_ethernet_init()
10.6.6. tse_mac_close()
10.6.7. tse_mac_raw_send()
10.6.8. tse_mac_setGMII mode()
10.6.9. tse_mac_setMIImode()
10.6.10. tse_mac_SwReset()
Visible to Intel only — GUID: bhc1410931508020
Ixiasoft
5.1.4.9. IP Payload Alignment
The network stack makes frequent use of the IP addresses stored in Ethernet frames. When you turn on the Align packet headers to 32-bit boundaries option, the MAC function aligns the IP payload on a 32-bit boundary by adding two bytes to the beginning of Ethernet frames. The padding of Ethernet frames are determined by the registers tx_cmd_stat and rx_cmd_stat on transmit and receive, respectively.
Bits | |||
---|---|---|---|
31...24 | 23...16 | 15...8 | 7...0 |
Byte 0 | Byte 1 | Byte 2 | Byte 3 |
Byte 4 | Byte 5 | Byte 6 | Byte 7 |
Bits | |||
---|---|---|---|
31...24 | 23...16 | 15...8 | 7...0 |
padded with zeros | Byte 0 | Byte 1 | |
Byte 2 | Byte 3 | Byte 4 | Byte 5 |