F-Tile Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 741328
Date 4/03/2023

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Document Table of Contents

1. About the F-Tile Triple Speed Ethernet Intel FPGA IP User Guide

Updated for:
Intel® Quartus® Prime Design Suite 23.1
IP Version 21.2.0
This user guide provides the features, architecture description, steps to instantiate, and guidelines about the Triple-Speed Ethernet Intel® FPGA IP for the Intel® Agilex™ (F-tile) devices.

Intended Audience

This document is intended for:

  • Design architect to make IP selection during system level design planning phase
  • Hardware designers when integrating the IP into their system level design
  • Validation engineers during system level simulation and hardware validation phase

Related Documents

The following table lists other reference documents which are related to the F-tile Triple-Speed Ethernet protocol.
Table 1.  Related Documents
Reference Description
Triple-Speed Ethernet Intel® FPGA IP Release Notes Lists the changes made for the Triple-Speed Ethernet Intel® FPGA IP in a particular release.

Acronyms and Glossary

Table 2.  Acronym List
Acronym Expansion
AXI ARM corporation's Advanced Extensible Interface
CDR Clock data recovery
CRC Cyclic redundancy code
CSR Control and Status Register
FPGA Field Programmable Gate Array
GMII Gigabit Media Independent Interface
MAC Media Access Control
MDIO Management data input/output
MII Media Independent Interface
PCS Physical coding sublayer
PHY Physical layer
PLL Phase-locked loop
PMA Physical medium attachment
RGMII Reduced Gigabit Media Independent Interface
TBI Ten-bit interface