F-Tile Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 741328
Date 4/03/2023

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8.2. Sharing PLLs in Devices with LVDS Soft-CDR I/O

For Intel® Agilex™ devices, you must adhere to the following LVDS soft-CDR placement guidelines to avoid Quartus design compilation fitter error:

  • In each GPIO bank of the Intel® Agilex™ FPGA device, there are two sub-banks. The top sub-bank has pin indexes from 48-95 and supports a maximum of 4 LVDS soft-CDR I/O. The bottom sub-bank has pin indexes from 0-47 and supports a maximum of 8 LVDS soft-CDR I/O.
  • For the exact location of the LVDS soft-CDR I/O pin, refer to the Intel® Agilex™ device pin-out files.
  • One Triple-Speed Ethernet IP cannot support LVDS soft-CDR I/O that has a mixture channel placement in both top and bottom sub-banks. You must constrain the LVDS soft-CDR I/O channel placement to either the top sub-bank or bottom sub-bank only.