Ashling* RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide

ID 730783
Date 5/13/2024
Document Table of Contents

6.7.2. Trace View

Table 13.  Trace View Information and Description
Trace Information Description
Timestamp The timestamp value received from the target
Cycles The CPU cycle count information. The cycle count is available from the target for a set of instructions only. Cycle count against an instruction represents the number of CPU cycles consumed for the set of instructions starting from the last cycle count received.
Context ID Context ID of the current execution. Context ID gives the information about the ASID and the current Process ID.
Core No Core index of the core executing the trace data.
Address The instruction address executed by the CPU.
Opcode Opcode of the executed instruction.
Disassembly Disassembly of the executed instruction.
Source Line Source Line corresponding to the instruction execution.

Example Use Case: Disassembly View

Double click the trace row to highlight the corresponding source line and disassembly in Source and Disassembly view. Refer Figure Trace View and the following figures for more details.
Figure 40. Source Highlighting — Debug and Disassembly Tab
Figure 41. Source Highlighting — main.c Tab