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1. About the RiscFree* IDE
2. Installation and Setup
3. Getting Started with RiscFree* IDE
4. Debug Setup for Nios® V Processor System
5. Debug Setup for Arm* Hard Processor System
6. Debugging with RiscFree* IDE
7. Debugging with Command-Line Interface
8. Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide Archives
9. Document Revision History for the Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide
A. Appendix
6.1. Debug Features in RiscFree* IDE
6.2. Processor System Debug
6.3. Heterogeneous Multicore Debug
6.4. Debugging µC/OS-II Application
6.5. Debugging FreeRTOS Application
6.6. Debugging Zephyr Application
6.7. Arm* HPS On-Chip Trace
6.8. Debugging the Arm* Linux Kernel
6.9. Debugging Target Software in an Intel® Simics Simulator Session
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6.3. Heterogeneous Multicore Debug
Heterogeneous multicore debugging is a method where you can debug two or more cores that differ in architecture or micro-architecture ( Nios® V processor core and Arm* HPS core) simultaneously in the same integrated development environment.
By using heterogeneous multicore debugging, you can do the following:
- Simultaneously debug the entire integrated system in a single IDE.
- Real-time control of multiple processor cores that interact with each other.
The example uses Nios® V processor "Hello World" project and HPS design example provided by Ashling.