Ashling* RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide

ID 730783
Date 5/13/2024
Document Table of Contents

5.3. Setting Debug Configurations and Downloading Arm* HPS Project Using RiscFree* IDE

To debug the project, follow these steps:

  1. Right-click the project directory and select Debug > Debug Configurations.
  2. Select Ashling Arm Hardware Debugging > cortex-a53-sum. Ensure the Project and C/C++ Application match with your project name and your project .elf file respectively.
  3. Under the Debugger tab, set these settings:
    • Debug probe: Agilex SI/SoC Dev Kit — Select the connected device
    • Transport type: JTAG
    • JTAG/SWD frequency: 16 MHz
    • Core selection: Can select any core between 0 to 3
    Figure 10. Debugger Settings for Agilex® 7 Arm* Cortex* -A53 Core
    Note: The default settings for the current example design in the RiscFree* IDE are configured based on Agilex® 7 device.

    If you are using a different Arm* architecture, select the Arm* GNU debugger (GDB) (select GDB Client Setup > Executable name) manually.

    • 64-bit ELFs: ${eclipse_home}/../toolchain/Arm/aarch64-none-elf/bin/aarch64-none-elf-gdb.exe
    • 32-bit ELFs: ${eclipse_home}/../toolchain/Arm/arm-none-eabi/bin/arm-none-eabi-gdb.exe
  4. Click Debug. RiscFree* IDE downloads the program to the target and you can find the console prints as shown in the following diagram.
    Figure 11.  RiscFree* IDE after Program is Downloaded and System is Ready for Debug